Toggle navigation
HN
Paper
All
Show
Ask
Jobs
Top stories
Today
Last 7 days
Last months
This year
Stats
Stories by matt_d
Publication Trends at ISCA (International Symposium on Computer Architecture)
3 points
matt_d
2019-08-02T16:04:55Z
www.sigarch.org
Practical Byte-Granular Memory Blacklisting Using Califorms
1 points
matt_d
2019-08-02T08:15:27Z
arxiv.org
Looking inside a 1970s PROM chip that stores data in microscopic fuses
7 points
matt_d
2019-07-30T16:20:03Z
www.righto.com
Nifty Features of the ARM Architecture
2 points
matt_d
2019-07-30T15:22:35Z
www.smart-cactus.org
CSRTale #13: Formal verification of strong eventual consistency
2 points
matt_d
2019-07-30T15:01:30Z
medium.com
Writing efficient free variable traversals – The Glasgow Haskell Compiler
3 points
matt_d
2019-07-30T09:23:37Z
www.haskell.org
IETF 105: Technology Deep Dive: How Network Interface Cards (NICs) Work Today
1 points
matt_d
2019-07-29T12:31:28Z
www.youtube.com
Combinatorial Register Allocation and Instruction Scheduling
2 points
matt_d
2019-07-27T13:51:43Z
arxiv.org
NDA: Preventing Speculative Execution Attacks at Their Source [pdf]
2 points
matt_d
2019-07-26T20:59:24Z
www.ofirweisse.com
Trip C++ Standards Meeting in Cologne, July 2019
1 points
matt_d
2019-07-26T14:40:11Z
botondballo.wordpress.com
Dynamic Languages and Parallelism: How to Go from Broken/Slow to Safe&Efficient?
1 points
matt_d
2019-07-22T16:19:14Z
www.youtube.com
Saving the World from Spreadsheets [video]
142 points
matt_d
2019-07-21T12:44:27Z
www.youtube.com
2019-07 Cologne ISO C++ Committee Trip Report: The C++20 Eagle has Landed
2 points
matt_d
2019-07-20T11:48:54Z
old.reddit.com
Pointer Tagging for Memory Safety
5 points
matt_d
2019-07-19T18:51:55Z
www.microsoft.com
A Golden Age of Hardware Description Languages
2 points
matt_d
2019-07-19T13:11:16Z
doi.org
Idris 2: Type-Driven Development of Idris – Curry On 2019 – Edwin Brady
5 points
matt_d
2019-07-18T19:40:48Z
www.youtube.com
Teaching Your SMT Solver Probability Theory
1 points
matt_d
2019-07-17T20:58:49Z
barghouthi.github.io
Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit
2 points
matt_d
2019-07-16T18:36:10Z
labs.domipheus.com
The dangers of conditional consistency guarantees
5 points
matt_d
2019-07-15T16:45:04Z
dbmsmusings.blogspot.com
Learning Key-Value Store Design
2 points
matt_d
2019-07-15T16:28:37Z
arxiv.org
83
84
85
86
87
88
89
90
91
92