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marcux95
Tiny-Vedas: RISC-V Infrastructure for AI Accelerator Design [pdf]
1 points
marcux95
2026-09-24T19:44:41Z
siliscale.com
Tiny-Vedas: a generic accelerator interface for RISC-V, from PyTorch op to GDS
2 points
marcux95
2026-09-18T17:11:27Z
github.com
1 points
marcux95
2026-01-01T20:07:14Z
news.ycombinator.com
1 points
marcux95
2025-12-27T16:34:54Z
news.ycombinator.com
1 points
marcux95
2025-11-26T18:48:38Z
news.ycombinator.com
1 points
marcux95
2025-11-15T17:27:55Z
news.ycombinator.com
1 points
marcux95
2025-11-09T17:27:31Z
news.ycombinator.com
1 points
marcux95
2025-11-06T19:55:23Z
news.ycombinator.com
1 points
marcux95
2025-10-25T08:53:58Z
news.ycombinator.com
My Mental Sanity Script on OpenWRT
1 points
marcux95
2025-10-01T03:07:56Z
gist.github.com
1 points
marcux95
2025-07-13T23:45:28Z
news.ycombinator.com
ECC SystemVerilog Generator
7 points
marcux95
2025-07-07T01:55:30Z
github.com
1 points
marcux95
2025-06-28T16:12:02Z
news.ycombinator.com
1 points
marcux95
2025-06-21T17:44:16Z
news.ycombinator.com
How to Compile a Large Language Model (LLM) to RISC-V
4 points
marcux95
2025-06-21T17:11:38Z
siliscale.com
1 points
marcux95
2025-05-01T00:49:31Z
news.ycombinator.com
1 points
marcux95
2025-04-05T02:29:29Z
news.ycombinator.com
1 points
marcux95
2025-03-20T16:38:10Z
news.ycombinator.com
1 points
marcux95
2025-03-16T23:29:04Z
news.ycombinator.com
RISC-V Processor Design – Lec 6 – EXU and Co-Simulation
5 points
marcux95
2025-03-12T02:17:48Z
news.ycombinator.com