Stories by godelmachine

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism

High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder

FlashAbacus: A Self-Governing Flash-Based Accelerator for Low-Power Systems

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost

Flexible-Latency DRAM: Exploiting Latency Variation in Modern DRAM Chips

Voltron:Trade-Offs in DRAM Chips to Improve Energy Eciency

LISA: Increasing Connectivity in DRAM for Fast Data Movement and Low Latency

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure

Read Disturb Errors in MLC NAND Flash Memory

Exploiting and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming

RowClone: Accelerating Data Movement and Initialization Using DRAM

Parallel Programming for FPGAs

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

Exploiting Row-Level Temporal Locality in DRAM to Reduce Memory Access Latency

Hybrid CMOS-CNFET Based NP Dynamic Carry Look Ahead Adder

Hierarchical Temporal Memory Using Memristor Networks: A Survey

Efficient Design of Hardware-Enabled Recurrent Neural Networks

Pushing the limits of optical information storage using deep learning

Progressive growing of GANs for improved quality, stability, and variation

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