Stories by cdr

Vector Models for Data-Parallel Computing (1990) [pdf]

SWAR UTF-8 Validation with the hidden RISC-V gem xperm4

Akeana Exits Stealth Mode with Comprehensive RISC-V Processor Portfolio

Gf2p8affineqb: Int8 Shifting

RISCVuzz: Discovering CPU Vulnerabilities via Differential Hardware Fuzzing [pdf]

Convex Architecture Handbook 1984 [pdf]

ARM's Scalable Vector Extensions: A Critical Look at SVE2 for Integer Workloads

A simple superscalar out of order RISC-V (micro)processor

Decapsulating the CH32V203 Reveals a Separate Flash Die

The Improved RISC-V Specification (latest WIP draft)

A vegan cheese beat dairy in a big competition. Then the plot curdled

Superfood protein pulled out of thin air scales up production

Imagination APXM-6200 RISC-V CPU

How to Design an ISA

Optimize sgemm on RISC-V platform

RISC-V Optimization Guide

Vectorizing Unicode conversions on real RISC-V hardware

Transposing a Matrix using RISC-V Vector

37C3: Writing secure software using my blog as example [video]

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