Stories by matt_d

The VexRiscV CPU – A New Way to Design

Type erasure and reification

A Highly Productive Implementation of an Out-Of-Order Processor Generator

Reconfigurable Computing at Hyperscale [video]

Making Memories: Clojure for Hardware Engineers (And Others)

SIMD-Visualizer: A tool to graphically visualize SIMD code

How to design co-programs

Glow: LLVM-based machine learning compiler – 2018 LLVM Developers’ Meeting

Diagrammatic Execution Models for Functional Languages – Lambda World 2018

Deep Learning Inference in Facebook Data Centers

OOPSLA 2018 Videos

How many uops are there?

Time is Partial: distributed consistency models and weak memory models

Programming Abstractions and Synthesis-Aided Compilation for Emerging Computing

A Systematic Evaluation of Transient Execution Attacks and Defenses

Lambda World 2018 – What FP Can Learn from Smalltalk by Aditya Siram

Trip report: Fall ISO C++ standards meeting

Zippers for non-inductive types

Transformations of High-Level Synthesis Codes for High-Performance Computing

ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS

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