Stories by hasheddan

RISC-V Acquire and Release Semantics

RISC-V Preserved Program Order: Rule 1

Rwasa: An Nginx Competitor Written in x86_64 Assembly

RISC-V Weak Memory Ordering

Messing with the Recipe

The Ten Million Room Hotel

Dyn async traits, part 7

Integer Bugs I Have Found

RISC-V Multiply Only Extension (Zmmul)

Rust and Valgrind

The Universal Control Plane – Crossplane Composition

Exploring RISC-V Privilege Levels

Instruction Address Misaligned Exceptions in RISC-V

RISC-V Svinval Extension

Do we need a link step?

Don’t Shell Out

New RISC-V Svnapot Extension

Best of 2021 in Tech Talks

Eurorack CPU

Making a CPU Using an Analog Modular Synthesizer

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